In recent years, with the advances made in the miniaturization of electronic devices, integration densities of IC (SSI, MSI, LSI, and VLSI) chips have been greatly increased. In mounting of semiconductor devices, such as ICs, onto a substrate, the distance (pitch) between electrode bumps has been reduced while the number of input/output(I/O) terminals has been increased. In card type calculators and IC cards, a demand has arisen for developing low-profile products which require short pitches.
Wireless bonding, such as tape automated bonding (TAB) and flip chip, can advantageously realize collective bonding of bumps with high-precision alignment between bumps, low-profile automatic mounting of semiconductor elements and high reliability. Therefore, wireless bonding has become a mainstream mounting techniques for IC chips.
In performing wireless bonding, these electrode bumps are generally formed on a substrate or an IC chip. The known bumps and methods of forming them suffer from several drawbacks. It is difficult to obtain a significant bump height without affecting bump series impedance and inductance. Obtaining a bump aspect ratio of greater than 1.5:1 is difficult if not impossible to achieve using present methods of bump formation such as, conventional one-step photolithographic bumping and liquid metal ion source bumping processes. A further problem is temperature coefficient of expansion (TCE) mismatch between the substrate and the semiconductor die mounted to the substrate. For example, the IBM C4 process is not optimal for mounting semiconductor die that are greater than 600 mils because of TCE mismatch. This problem is exacerbated in I/O pads located in corners of the substrate because shear forces due to TCE mismatch are in multiple directions.